module  rbve_line_16#(
    parameter SUBR = 16,
    parameter RULE_SUM= 32,
    parameter LOG2R  = 5,
    parameter DEPTH  = 16
    )
   (
    input wire clk,
    input wire rst_n,
    input wire lookup_en,//一个周期就可以了
    input wire en_in,
    input wire mod_en,
    input wire[8:0] addr_loc,
    input wire[127:0] cpu_data,
    output reg lookup_done,
    input wire[0:RULE_SUM-1] match_in,
    input wire[SUBR-1:0] range,
    output reg[0:RULE_SUM-1] match_out,
    output wire match_is,
    output wire[127:0] cpu_data_o
    );

//*******************
//DEFINE LOCAL PARAMETER
//*******************
//parameter(s)

             
                                    

 integer i;

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS
reg lookup_en_ff2,lookup_en_ff1;
reg[RULE_SUM-1:0] ram [DEPTH-1:0];
reg[RULE_SUM-1:0] ram_out;
reg[0:RULE_SUM-1] match_in_ff;
reg[31:0] cpu_data_o_r;
//WIRES
wire[3:0] addr_loc1;
wire[31:0] cpu_data1;
//*********************
//INSTANTCE MODULE
//*********************


//*********************
//MAIN CORE
//*********************

always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      begin
      lookup_en_ff1  <= 1'b0;
      lookup_done    <= 1'b0;  
      end
    else 
      begin 
      lookup_en_ff1  <= lookup_en;
      lookup_done    <= lookup_en_ff1;
      end 
  end
always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      match_in_ff <= 0;
    else
      match_in_ff <= match_in;
  end
always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      ram_out <= 0;
    else if(lookup_en)
      ram_out <= ram[range];
    else 
      ram_out <= ram_out;
  end
always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      for(i=0;i<=DEPTH-1;i=i+1)
        ram[i] <= 0;
    else if(mod_en)
     ram[addr_loc1]<=cpu_data1; 
  end
always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
     cpu_data_o_r <= 32'h0;
    else 
     cpu_data_o_r <= ram[addr_loc1];
  end
always@(posedge clk or negedge rst_n)
  begin
    if(~rst_n)
      match_out <= 0;
    else if(lookup_en_ff1)
      match_out <= ram_out & match_in_ff;
    else 
      match_out <= 0;
  end
assign match_is = (match_out==0)?1'b0:1'b1;
assign addr_loc1 = addr_loc[3:0];
assign cpu_data1 = cpu_data[31:0];
assign cpu_data_o = {96'h0,cpu_data_o_r};
//*********************
endmodule    // hookup byte controller block